Papers
A High Performance Binary TO BCD Converter for Decimal Multiplication
Jairaj Bhattacharya, Aman Gupta, Anshul Singh " A High Performance Binary to BCD Converter for Decimal Multiplication" VLSI-DAT 2010, Hsinchu, Taiwan, April 26-29,2010
Decimal data processing applications have grown exponentially
in recent years thereby increasing the need to have hardware support for decimal arithmetic. Binary to BCD conversion forms the basic building block of decimal digit multipliers. This paper presents novel high speed low power architecture for fixed bit binary to BCD conversion which is at least 28% better in terms of power-delay product than the existing designs.
LikeA More Precise Model of Noise Based PCMOS Errors
Arun Bhanu, Mark S. K. Lau, Keck-Voon Ling, Vincent J. Mooney III, Anshul Singh "A More Precise Model of Noise Based PCMOS Errors", DELTA 2010,Ho Chi Minh City, January 13-15, 2010
In this paper we present a new model for characterization of probabilistic gates. While still not main stream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder.Our contribution helps account for the filtering effect seen in noise based PCMOS in a novel way. The characterization proposed here can enable accurate multi- bit models based on fast mathematical extrapolation instead of expensive and slow HSPICE simulations.
A High Performance Unified BCD and Binary Adder/Subtractor
Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M.B. Srinivas, "A High Performance Unified BCD and Binary Adder/Subtractor," isvlsi, pp.211-216, 2009 IEEE Computer Society Annual Symposium on VLSI, 2009
Decimal data processing applications have grown exponentially in recent years thereby increasing the need to have hardware support for decimal arithmetic. In this paper, an improved architecture for efficient Binary Coded Decimal (BCD) addition/subtraction is presented that performs binary addition/subtraction without any extra hardware. The architecture works for both signed and unsigned numbers. The design is runtime reconfigurable and maximum utilization of the hardware is a feature of the architecture. Simulation results show that the proposed architecture is at least 32% better in terms of power-delay product than the existing designs.
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